Sub-micron high input voltage tolerant input output (I/O) circuit

ABSTRACT

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. Non-Provisional applicationSer. No. 11/182,646, filed Jul. 14, 2005, now U.S. Pat. No. 7,292,072,which is a continuation of U.S. Non-Provisional application Ser. No.10/621,005; filed Jul. 16, 2003, now U.S. Pat. No. 6,949,964, which is adivisional of U.S. Non-Provisional application Ser. No. 10/043,788,filed Jan. 9, 2002, now U.S. Pat. No. 6,628,149, which claims benefit toU.S. Provisional Application No. 60/260,582, filed Jan. 9, 2001, andU.S. Provisional Application No. 60/260,580, filed Jan. 9, 2001, all ofwhich are hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuits (ICs), such asinterface circuits, that are designed having reduced feature sizes, forexample, 0.13 gm. More particularly, the invention relates to ICs thatinclude interfaces (such as input/output (I/O) circuits) that arecapable of interfacing with comparatively high-voltage signals fromother sources, for example a 3.3 volt IC interfacing with signals from a5 volt IC, or any other disparate ranges. Moreover, the inventionrelates to integrated circuits in which the semiconductor devices arebiased such that the stress across the gate-oxides and junctions, aswell as the leakage currents, are maintained at tolerable levels.

2. Background Art

The trend in CMOS-based processing technology is to produce integratedcircuit (IC) cores having a higher density of semiconductor devices,such as transistors, and faster clock rates than their predecessors. I/Ocircuits, which electrically couple an IC core to external components,are accessed through I/O circuit pads that surround the IC core. The ICcore and the I/O circuit pads are generally fabricated from the sameprocessing technology. There is however no requirement that theycomprise the same technology and hybrid circuits are known in the art.The inventive concepts herein are applicable to a variety of fabricationtechnologies.

The performance of the IC cores may generally be improved by shrinkingthe feature sizes of the semiconductor devices, for example field-effecttransistors (FETs). Unfortunately, reducing the IC feature sizes mayproportionally decrease the maximum operating voltage that thesemiconductor devices within the IC can withstand. For example, an I/Ocircuit pad, fabricated from a CMOS process having 0.30 micron features,typically withstands a maximum operating voltage of about 3.6 volts. Insuch a case the maximum operating voltage of the I/O circuit pad isinsufficient to drive the external components which have a highervoltage requirement, such as 5 volts. Furthermore, if the IC isinterfaced with a greater than the maximum operating voltage, the IC mayfail.

One way to attempt to resolve such requirements of circuits withmismatched voltage requirements is to increase the robustness of thefabrication process, for example by increasing the thickness of thegate-oxide layer of the semiconductor devices which comprise the ICcircuitry. A thick gate-oxide layer may provide semiconductor devices,such as FETs, with the ability to support a higher voltage requirement.However, this voltage robustness is commonly accompanied by a decreasesthe performance of the IC, because the thick gate-oxide layer reducesthe overall gain of the devices which comprise the IC. Reducing the gainminimizes the benefit which occurs by reducing the feature size.

Other attempts have included increasing the complexity of the CMOSfabrication process so there are multiple sets of devices where each setmeets different voltage requirements. Each set of devices requires adifferent gate-oxide. Each additional gate-oxide requires a separatemask. The resulting hybrid process may significantly increase themanufacturing costs of the IC.

One way to avoid the drawbacks of the aforementioned processing-basedsolutions is to use a “level-shift” chip as an external component. TheIC core and the I/O circuits are fabricated from the same process. The“level-shift chip” may be fabricated from a process that supports thediscrete voltage requirement by stepping up the core output signals tosupport the discrete voltage range and stepping down the external drivesignals to support the IC core voltage range. Such a level-shift chipcan be a waste of much needed space on a crowded printed circuit boardand may degrade performance.

An I/O circuit that transforms voltages between different voltage levelswithout degrading the overall performance of the integrated circuit andmaximizing use of space on the printed circuit board or multi-chipsubstrate may be beneficial. It would be a further benefit if such anI/O circuit could use voltages presented at the I/O circuit in order toprovide such protective biasing.

Commonly an I/O power supply may vary ±10% and may vary significantlymore during transient conditions. When the I/O power supply varies,circuits may have higher stress on the gate-oxides of the devices in theI/O circuit, such stresses may not be desirable in many processtechnologies. It may be desirable to provide bias voltages to variousdevices in the I/O circuit such that the device gate-oxide is protectedfrom high-voltages under various conditions of operation even when thepower-supply voltage varies by a large amount.

Embodiments of the present invention may be optimized, for example where5 volt input tolerance is required, even when the power supplies arevarying in steady state by ±10%.

Embodiments of the present invention are illustrated in an optimizedform for I/O circuits where a 5 volt ±10% input tolerance is requiredfor normal operating range. Additionally the inventive concepts hereinare described in terms of CMOS (Complimentary Metal Oxide Semiconductor)integrated circuits. Those skilled in the art will readily appreciatethe fact that techniques described with respect to CMOS ICs are readilyapplicable to any circuits having disparate power supply and/or drivesignal requirements for different portions of the circuitry. The CMOSexample chosen is one likely to be familiar to those skilled in the art.There is, however, no intent to limit the inventive concepts to CMOS ICsas the techniques are equally applicable to a wide variety of integratedcircuit fabrication techniques.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of the invention includes an integrated circuithaving a four device input output circuit in a push pull configuration.Two of the devices, termed upper devices, comprise PMOS (P-Channel MetalOxide Semiconductor) devices and two of the devices, termed lowerdevices, comprise NMOS (N-channel Metal Oxide Semiconductor) devices.The devices are biased to eliminate hazardous voltages across devicejunctions and to reduce the magnitude of the voltage being passed on tothe core circuitry. The biases are derived from the input output stateof the circuit and the voltage presented to the I/O circuit connection(V_(PAD)) Additionally PMOS device well bias voltage may be developedbased on V_(PAD).

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

Other features and advantages of the invention will become apparent froma description of the following figures, in which like numbers refer tosimilar items throughout.

FIG. 1 is a graphic illustration of an exemplary environment in whichembodiments of the invention may be utilized.

FIG. 2 is a graphical illustration of a prior art input output circuitand connection.

FIG. 3 is a schematic of a portion of a CMOS (Complimentary Metal OxideSemiconductor) input output circuit in which single push pull outputdevices, as illustrated in FIG. 2, have been replaced by two deviceseach.

FIG. 4 is input output circuit, including a well biasing circuit,according to an embodiment of the invention.

FIG. 5 is a graph illustrating the relationship between well voltage andpad voltage for the input (or a tristate) mode, according to anembodiment of the invention.

FIG. 6 is a block diagram of I/O circuitry biasing according to anembodiment of the invention.

FIG. 7 is a graphical representation of a bias voltage (V_(Gp1)) as afunction of pad voltage (V_(PAD)), according to an embodiment of theinvention.

FIG. 8 is a graphical illustration of a portion of a circuitconfiguration used to provide the pad voltage to the core circuitry,according to an embodiment of the invention.

FIG. 9A is a schematic diagram of the generation of Bias_Mid voltage,according to an embodiment of the invention.

FIG. 9B is a schematic diagram of an alternative embodiment for thegeneration of Bias_Mid voltage, according to an embodiment of theinvention.

FIG. 9C is a schematic diagram of yet another alternative embodiment forgeneration of Bias_Mid voltage, according to an embodiment of theinvention.

FIG. 10 is a schematic diagram of an exemplary well biasing circuit,according to an embodiment of the invention. FIG. 11A is a schematicdiagram of a circuit used to generate V_(Gp1).

FIG. 11B is a schematic diagram illustration of the generation ofV_(DDO)−V_(TP) depicted in FIG. 11A.

FIG. 11C is a graph illustrating the relationship between Bias_Mid andV_(PAD) according to an embodiment of the invention.

FIG. 11D is a schematic diagram depicting an exemplary illustration of atransistor implementation of block 901.

FIG. 12 is a schematic diagram of a circuit that may be used to preventpower on stress of devices, according to an embodiment of the invention.

FIG. 13 is a circuit and block diagram of a portion of an over voltageprotection circuit.

FIG. 14 is a schematic diagram illustrating a modification of FIG. 9A.

FIG. 15 is a schematic diagram illustrating a transistor implementationof block 1401.

FIG. 16 is a schematic diagram illustrating a transistor implementationof FIG. 14.

FIG. 17 is a schematic diagram of a circuit that may be used to preventstress on devices when voltage spikes appear at an I/O pad.

FIG. 18 is a schematic diagram of a circuit including several previouslyillustrated embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a graphic illustration of an exemplary environment in whichembodiments of the invention may be utilized. In FIG. 1 a personalcomputer system is represented generally at 101. Within the computersystem is circuit board 103 on which a CPU integrated circuit chip 105is mounted. The CPU is a type which uses 3.3 volts as its supplyvoltage. A keyboard interface integrated circuit chip 107 is alsomounted on circuit board 103. The keyboard interface integrated circuituses a supply voltage of 5.0 volts. The CPU 105 is coupled to theKeyboard chip 107. The CPU 105 may be of a type which containsintegrated devices that may be damaged by interfacing with a devicehaving a higher supply voltage. Because of the disparity in supplyvoltages that may exist in such situations an output circuit which cancompensate for the higher interface voltages may be useful.

FIG. 2 is a graphical illustration of a prior art input output circuitand connection. A common input output circuit comprises a pull updevice, such as PMOS (P-channel Metal Oxide Semiconductor) device 215and a pull down device, such as NMOS (N-channel Metal OxideSemiconductor) device 217, such as illustrated in FIG. 2. Devices 215and 217 are coupled together at an input/output (I/O) pad 219. Thesubstrate for the NMOS device is commonly coupled to ground potential,e.g. as shown at 221. The substrate for the NMOS device is typically asubstrate which is common for the entire integrated circuit chip onwhich it resides. PMOS devices are commonly fabricated in their ownisolated well.

In deep submicron fabrication, the component integrated devices cantolerate only limited differential voltages across their junctions.Commonly the voltage which can be tolerated across the junctions is onthe order of 2.5 Volts.

In the Illustration of FIG. 2 pad 219 interfaces to a 5 volt circuit,and hence the pad may commonly see voltages in the neighborhood of 5.5volts. A 5 volt signal applied to pad 219 may stress devices within thechip 105. For example if gate 205 of device 217 is at a zero voltpotential then the voltage across the 205-203 gate-oxide can exceed 5volts, thereby stressing device 217. For this reason more than onedevice may be used to divide the voltages in pull up and pull down I/Ocircuits.

FIG. 3 is a schematic of a portion of a MOS (Metal Oxide Semiconductor)input output circuit in which each push pull output device illustratedin FIG. 2 has been replaced by two devices. That is output device 215has been replaced by devices 301 and 303 and device 217 has beenreplaced by devices 305 and 307. By replacing devices 215 and 217 by twodevices each, the output voltage appearing at pad 309 may be safelydivided over the two upper (301 and 303) and the two lower (305 and 307)I/O devices. The middle NMOS device 303 and the middle PMOS device 305have their gates biased to intermediate potentials to avoid excessivevoltages under various I/O pad, 309, voltages.

FIG. 4 is input output circuit 404, including a well biasing circuit,according to an embodiment of the invention. Devices 301 and 303 arefabricated in wells, illustrated schematically as 400 and 402, which areessentially at a floating potential. Because devices in wells atfloating potential can have problems, such as device latch up, wells maycommonly be coupled to a known bias voltage. The wells of devices 301and 303 are coupled to the highest circuit potential available usingwell biasing circuit 401. The inputs to the well biasing circuit are thepad voltage present on input output pad 309, V_(DDO) and voltage V_(Gp1)which are illustrated in FIG. 7.

During the operation of input output circuit 404, in an output mode(when pad 309 is in an output driving mode), wells 400 and 402 arecoupled to V_(DDO). When the pad 309 is in an input mode, the wellvoltage depends upon the pad voltage. In the output enable modeV_(well)=V_(DDO).

When input output circuit 404 is in an input mode (when pad 309 is in aninput mode), V_(well) depends on both the input (Pad) voltage V_(PAD)and V_(DDO). If V_(PAD) is less than V_(DDO) when input output circuit404 in the input mode then V_(well)=V_(DDO). If V_(PAD) is greater thanV_(DDO) then V_(well)=V. A graph of this relationship is illustrated inFIG. 5.

FIG. 5 is a graph illustrating the relationship between well voltage andpad voltage for the I/O circuit in an input (or a tristate) condition.As can be seen from the graph, if the pad voltage is less than V_(DDO)then the well voltage is equal to V_(DDO). If the pad voltage is greaterthan V_(DDO) then the well voltage is equal to the pad voltage. The wellbias can thereby be changed according to changing circuit conditions.

FIG. 6 is a block diagram of I/O circuitry 600 biasing according to anembodiment of the invention.

When I/O circuitry 600 is in the input mode, first bias circuit 407 tiesgate 403 of device 301 to V_(DDO). In the output mode device 301 iscontrolled by an input from first bias circuit 407 according to whethera high or low value is being output on the pad 309.

In the input mode second bias circuit 405 provides gate voltage V_(Gp1)to the gate of output device 303. The gate voltage V_(Gp1) provided tothe gate of output device 303 varies from an intermediate power supplyvoltage, such as V_(DDC) being equal to 1.2 volts, and the pad voltagepresented to the circuit at input output pad 309. Such biasing preventsdevice 303 from being damaged due to a voltage potential across itsjunctions.

FIG. 7 is a graphical representation of V_(Gp1) bias voltage as afunction of pad voltage (V_(PAD)). If V_(PAD) is less than V_(DDO), thenV_(Gp1) provided to the gate of output device 303 is equal to theintermediate supply voltage V_(DDC). If V_(PAD) is greater than V_(DDO)then V_(Gp1) provided to the gate of output device 303 is equal to V. Insuch a manner the voltage between the gate of device 303 and pad 309 canbe kept in a safe range to prevent damage to the junction.

To summarize the operation of the circuit of FIG. 6, when the circuit600 is in an output mode: The well biasing circuit 401 ties the wells ofdevices 301 and 303 to V_(DDO). The gate of the lower PMOS device 307 istied to an intermediate voltage, such as V_(DDC)=1.2 Volts. The gate ofupper NMOS device 305 is tied to an intermediate voltage, such asV_(DDP)=2.5 Volts.

When the circuit 600 is in not in output mode, that is in the tri_stateor input mode then upper PMOS device 301 and lower NMOS device 307 areturned off and devices 303 and 305 are turned on to divide the voltagesof the output circuit.

The gate voltage of the upper NMOS device 305 is controlled by thirdbias circuit 409. Third bias circuit 409, when in an input or tristatemode, will increase the base voltage when the pad voltage increasesbeyond a certain threshold, for example V_(DDP) equal to 2.5 Volts.

Fourth bias circuit 411 works in a similar fashion to first bias circuit407. Both bias circuits 407 and 411 work in a digital mode, eitherproviding a first or second voltage depending on the required I/O pad309 output voltage. In a first mode of operation first bias circuit 407switches between a first voltage V_(DDO) and a second lower voltageV_(DDC). Gate bias circuit 411 switches between providing V_(DDP) andground potential to the gate of device 307.

FIG. 8 is a graphical illustration of a circuit configuration used toprovide the pad voltage to the core circuitry. The Vppm input is coupledto the core circuitry 803 through an NMOS device 801. The gate of NMOSdevice 801 accepts Bias_Mid as its control voltage. Such an arrangementprotects the gate source voltage of device 801 and also prevents largevoltages from the input from bing coupled into the core circuitry whenit is in the input, (tristate) or output conditions.

One facet of the I/O system comprising devices 301, 303, 305 and 307 isthat any number of such devices may be added in parallel, in order toprovide any level of drive signals needed.

FIG. 9A is a schematic diagram illustrating how Bias_Mid voltage isgenerated. Block 901 is a switching circuit that switches its Bias_1output between voltages V_(DDO) (3.3 Volts nominally in the presentembodiment) and V_(DDC) (1.2 Volts nominally in the present embodiment).Device 905 is a PMOS device as are devices 907 and 909. Device 907 turnson when the output is enabled or the V_(PAD) is low. When device 907 isturned on, Bias_Mid is coupled to V_(DDP). When output is not enabledi.e. the pad is in the tri-state (input only) mode and V_(PAD) is high,then Bias_1 is equal to V_(DDO) and device 905 charges point 911 toBias_1 minus V_(TP), where V_(TP) is the threshold of device 905, andaccordingly is the voltage dropped across device 905. If Bias_Mid isgreater than the sum of V_(DDP) and V_(TP), then device 909 will draincurrent from node 911 such that the sum of V_(DDP) Plus V_(TP) is themaximum value for Bias_Mid. Bias_Mid is always between (V_(DDP)+V_(TP))and (V_(DDO)−V_(TP)) , whether (V_(DDP)+V_(TP)) or (V_(DDO)−V_(TP)) islarger. A typical value of the threshold voltage V_(TP) is 0.5 volts.The actual value of Bias_Mid will be determined by the relative sizes ofdevices 907 and 909.

FIG. 9B is a schematic diagram of an alternate embodiment illustratinghow Bias_Mid voltage is generated in an alternate embodiment. Block 901is a switching circuit that switches its Bias_1 output between voltagesV_(DDO) (3.3 Volts nominally in the present embodiment) and V_(DDC) (1.2Volts nominally in the present embodiment). Device 905 is a PMOS deviceas is device 907. Device 909B is a NMOS device. Device 907 turns on whenthe output is enabled or the V_(PAD) is low. When device 907 is turnedon, Bias_Mid is coupled to V_(DDP). When output is not enabled i.e. thepad is in the tri_state (input only) mode and during this time when VppDis high, then Bias_1 is equal to V_(DDO) and device 905 charges point911 to Bias_1 minus V_(TP), where V_(TP) is the threshold of device 905,and accordingly is the voltage dropped across device 905. If Bias_Mid isgreater than the sum of (V_(DDP)+V_(TP)) then device 909 b will draincurrent from node 911 such that (V_(DDP)+V_(TP)) is the maximum valuefor Bias_Mid. Bias_Mid is always between (V_(DDP)+V_(TN)) and(V_(DDO)−V_(TP)), whether (V_(DDP)+V_(TN)) or (V_(DDO)−V_(TP)) islarger. A typical voltage value for the threshold voltage V_(TP) is 0.5volts. The actual value of Bias_Mid will be determined by the relativesizes of devices 907 and 909 b.

FIG. 9C is a schematic diagram of yet another alternate embodiment forgeneration of Bias_Mid voltage. In this circuit Bias_Mid is always lessthan (V_(DDP)+V_(TP)) and greater than (V_(DDO)−V_(TN)).

FIG. 10 is a schematic diagram of an exemplary well biasing circuit,according to an embodiment of the invention. Device 1001, when turnedon, couples the I/O pad 309 to the well 1005. Device 1003, when turnedon, couples V_(DDO) to the well 1005. When Vww is less than V_(DDO) thegate source of device 1001 is less than the threshold voltage of device1001, and device 1001 is turned off. When V_(Gp1) is low (e.g. 1.2Volts) then device 1003 conducts, thereby tying the well 1005 toV_(DDO). When V_(PAD) is equal to V_(DDO) or greater then device 1001will begin to turn on, thereby coupling the well 1005 to V_(PAD).

FIG. 11A is a schematic diagram of a circuit used to generate V_(Gp1).Bias_1 switches between V_(DDO) (3.3 volts) and V_(DDC) (1.2 volts).Device 1101 couples Bias_1 to V_(Gp1), When bias_1 is 3.3 volts device1101 is off and when bias 1 is 1.2 Volts then V_(Gp1) is tied to 1.2Volts. When the V_(PAD) at 309 is greater than V_(DDO) device 1103begins to conduct, because the gate of device 1103 is tied to(V_(DDO)−V_(T)P),and V_(Gp1) is thereby coupled to V_(PAD).

FIG. 11B shows a circuit which may be used to generate (V_(DDO)−V_(TP)).The strong upper PMOS device charges the node 1150 to (V_(DDO) 31V_(TP)). In addition to the problems that may be caused when a lowersupply voltage chip is interfaced with a higher voltage chip “power onstress” problems, which may be caused when circuitry is turned on andthe supplies that provide protective biases are not yet up to their fullvoltage, may exist. In such a case a voltage present at an I/O pad maystress devices which are coupled to that I/O pad.

FIG. 11C is a graph illustrating the relationship between Bias_Mid andV_(PAD). Bias_Mid is set at 2.5 volts, and remains at 2.5 volts untilV_(PAD) increases beyond 2.5 volts. Thereafter Bias_Mid tracks increaseswith V_(PAD) and becomes equal to a higher voltage when V_(PAD)increases beyond a certain value.

FIG. 11D is a schematic diagram depicting an exemplary illustration of atransistor implementation of block 901.

FIG. 12 is a schematic diagram of a circuit that may be used to preventpower on stress of devices, according to an embodiment of the invention.The circuit illustrated in FIG. 12 may be used to generate the Bias_Midvoltage when V_(DDO) is not up to its nominal value. If Bias_Mid ispresent then devices 305 and 307, shown in FIG. 8, will be protectedfrom junction over voltage problems even though the voltages, whichordinarily would be used to generate Bias_Mid as explained in FIG. 9,are not present.

In FIG. 12 devices 1201, 1203, and 1205 are arranged as a series ofdiode coupled transistors such that a threshold voltage V_(TP) (in thepresent example equal to approximately 0.5 volts) is dropped across eachdevice when it is conducting. When device 1207 is conducting, the padvoltage, minus the threshold voltage of devices 1201, 1203, 1205 and1207, is coupled to Bias_Mid. Device 1207, in essence, acts as a switch.

As an example, assume that V_(DDO) is initially zero volts. Zero voltsat the gate of device 1209 turns it on. In such case point 1211 chargesto a potential close to the pad voltage, since device 1213 is off. Point1211 is coupled to the gate of device 1214 thereby turning device 1214off.

Since V_(DDO) is zero volts, PMOS device 1219 turns on, which leads thegate of device 1207 being coupled to Bias_Mid. This leads to couplingthe pad voltage, minus the threshold voltage of devices 1201, 1203, 1205and 1207 to Bias_Mid. When V_(DDO) is low, device 1215 provides acurrent leakage path for Bias_Mid to V_(DDC) or V_(DDP). When V_(DDO) islow, string 1217 turns on and the pad voltage is coupled to Bias_Mid.Devices 1220, 1221, 1223 and 1225 act as protection for device 1209 inthe instance where the V_(PAD) is high and V_(DDO) is low.

When V_(DDO) is high, point 1211 is tied to Bias_Mid because device 1213turns on. When V_(DDO) is high, device 1219 is turned off and device1213 is turned on, thus raising the potential at the base of device 1207to V_(PAD), thereby turning device 1207 off. Also device 1215 turns offwhen V_(DDO) is high.

FIG. 13 is a circuit and block diagram of a portion of an over voltageprotection circuit. Device 1001 provides a protection mechanism for thewell bias. If V_(DDO) is lower than the pad voltage by V_(TP) or morethen device 1001 will turn on. If device 1001 turns on then the well iscoupled, via device 1001, to the pad, and hence the well will be biasedto V_(PAD).

Similarly device 1301 is coupled between the pad and P_Gate, the gate ofPMOS device 303 shown in FIG. 6. The gate of device 1301 is biased sothat when V_(DDO) is lower than the pad voltage by V_(TP) or more, thendevice 1301 will turn on and couple P_Gate to the pad voltage, thereforeif V_(DDO) is low then P_Gate will not depend on V_(DDO) for it'svoltage level and instead will take the voltage level from the voltageon the pad.

FIG. 14 is a schematic diagram illustrating a modification of FIG. 9. InFIG. 14 block 901 is decoupled from the Bias_Mid signal when V_(DDO) islower than its nominal value. The decoupling is done by using block1401. When V_(DDO) is not up to its nominal value, the node V_pwr isdecoupled from V_(DDP) by using block 1401 as a switch. When V_(DDO) isup to its nominal value, the node V_pwr is coupled to V_(DDP) by usingblock 1401.

FIG. 15 is a schematic diagram illustrating a transistor implementationof block 1401. When V_(DDO) is greater than a certain value, NMOS 1507is turned on thereby connecting the gate of PMOS 1505 to V_(DDC).Connecting the gate of of PMOS 1505 to V_(DDC) turns on 1505 therebyconnecting V_pwr to V_(DDP) When V_(DDO) is less than a certain value,NMOS 1507 is turned off and PMOS 1506 is turned on thereby connectingthe gate of PMOS 1505 to Bias_Mid, thereby turning off PMOS 1505 anddisconnecting V_pwr from V_(DDP)

FIG. 16 is a schematic diagram illustrating a transistor implementationof the circuitry illustrated in FIG. 14.

FIG. 17 is a schematic diagram of a circuit that may be used to preventstress on devices when voltage spikes appear at an I/O pad. Whentransient voltages appear, the Bias_Mid voltage changes momentarily dueto the gate to drain overlap capacitance (Cgd) of the driver NMOS. Acapacitance (Cbm) is placed at the bias_mid node such that the transientvoltage at the pad (V_pad,transient) gets divided between Cgd and Cbmdepending on the ratio of the capacitances which gives the additionaltransient voltage on bias_mid (V_bm,transient):ΔAV _(—) bm,transient=(Cgd/(Cgd+Cbm)*ΔV_pad,transient.

Also, when transient voltages appear, the voltage V_(Gp1) on PMOS 207gate changes momentarily due to the gate to drain overlap capacitance(Cgdp) of the driver PMOS. A capacitance (Cgp) is placed at the PMOS 207gate node such that the transient voltage at the pad (V_pad,transient)gets divided between Cgdp and Cgp depending on the ratio of thecapacitances which gives the additional transient voltage on PMOS 207gate (V_(Gp1)+transient):Δ(VcP1+transient)=(Cgdp/(Cgdp+Cgp))*Δ(V pad,transient).

FIG. 18 is a schematic diagram of a circuit including several previouslyillustrated embodiments of the invention. The transistors illustrated inFIG. 18 are all 2.5 volt devices. The maximum output pad voltage is 3.6volts and the maximum input voltage is 5.5 volts. The typical values ofpower supplies are V_(DDO)=3.3 volts, V_(DDP)=2.5 volts, V_(DDC)=1.2volts, V_(SSC)=0 volts and V_(SSO)=0 volts. The operation of the circuitof FIG. 18 under various operating conditions is summarized below.

When the I/O pad 309 is in an output enabled mode (i.e. OE is high) themaximum pad voltage is V_(DDP). V_(Gp1) at the gate of PMOS device 303is coupled to V_(DDC) through NMOS transistors 1101 and 1801 andaccordingly PMOS device 303 is turned on. Block 901 generates an outputBias_1 voltage of V_(DDC) and accordingly PMOS device 907 is turned on,the steady state voltage of Bias_Mid is V_(DDP) and PMOS device 905 isturned off.

When the I/O pad 309 is output disabled (i.e. OE is low) and the padvoltage is below a predetermined value,then V_(Gp1) at the gate of PMOS303 is floating if the pad voltage is below V_(DDO). Block 901 generatesa output Bias_1 voltage of V_(DDC) and accordingly PMOS device 907 isturned on, the steady value of Bias_Mid voltage is V_(DDP), and PMOSdevice 905 is turned_off in this condition.

When the I/O pad 309 is output disabled (i.e. OE is low) and the padvoltage is above a predetermined value, then block 901 generates anoutput Bias_1 voltage of V_(DDO) and accordingly PMOS device 907 isturned_off, PMOS device 905 is is turned on, and the steady state valueof Bias_Mid is between (V_(DDO)−V_(TP)) as a minimum value and(V_(DDP)+V_(t)) as a maximum value, where V_(TP), and V_(t) are offsetvoltages due to the turn on threshold voltages of transistors 905 and909 b respectively. V_(GP1), at the gate of PMOS device 303 is coupledto the pad voltage if the pad voltage is greater than V_(DDO).

Capacitors C_(bm) and C_(gp) in FIG. 18 are used to insure that Bias_Midvoltage and V_(GP1) voltage, respectively, are kept at desirable levelswhen transient voltages appear at the pad as was described relative toFIG. 17.

1. A method for generating a bias voltage at a bias node using a biascircuit, the method comprising: accepting a pad voltage from aninput/output circuit node; accepting a power supply voltage; acceptingan intermediate voltage; providing a voltage derived from the powersupply voltage or the intermediate voltage to the bias node when thepower supply voltage is greater than a first predetermined value or theintermediate voltage is greater than a second predetermined value; andproviding a voltage derived from the pad voltage to the bias node whenthe power supply voltage is not greater than the first predeterminedvalue and the intermediate voltage is not greater than the secondpredetermined value.
 2. The method of claim 1, further comprisingproviding a voltage derived from the power supply voltage and theintermediate voltage to the bias node when the power supply voltage isgreater than the first predetermined value and the intermediate voltageis greater than the second predetermined value.
 3. A method forgenerating a bias voltage at a bias node using a bias circuit, themethod comprising: accepting a pad voltage from an input/output circuitnode; accepting a power supply voltage; providing a voltage derived fromthe power supply voltage to bias node when the power supply voltage isgreater than a predetermined value; and providing a voltage derived fromthe pad voltage to the bias node when the power supply voltage is notgreater than the predetermined value.
 4. The method of claim 3, whereinthe predetermined value is about 3.3 Volts.
 5. The method of claim 3,wherein the power supply voltage is accepted by a P-channel Metal OxideSemiconductor (PMOS).
 6. The method of claim 3, wherein the pad voltageis accepted by an N-channel Metal Oxide Semiconductor (NMOS).
 7. Themethod of claim 3, wherein the power supply voltage is accepted by aP-channel Metal Oxide Semiconductor (PMOS) and wherein the pad voltageis accepted by an N-channel Metal Oxide Semiconductor (NMOS).
 8. Themethod of claim 7, wherein the PMOS and the NMOS are connected at thebias node.
 9. An apparatus for generating a bias voltage at a bias node,the apparatus comprising: a first input for accepting a pad voltage froman input/output circuit; a second input for accepting an output enablesignal; a third input for accepting a first input voltage; and an outputcircuit for providing the first input voltage to the bias node when theoutput enable signal is at an enable value and for providing a voltagedepending on the pad voltage to the bias node when the output enablesignal is at a disable value.
 10. The apparatus of claim 9, furthercomprising: a fourth input for accepting a second input voltage, whereinthe output circuit provides a constant voltage equal to the first inputvoltage to the bias node until the pad voltage is equal to the firstinput voltage and provides an increasing voltage tracking the padvoltage when the pad voltage is not less than the first input voltagebut is less than the second input voltage minus an offset voltage. 11.The apparatus of claim 10, wherein the offset voltage is equal to athreshold voltage of a transistor.
 12. The apparatus of claim 10,wherein the offset voltage is equal to a threshold voltage of aP-channel Metal Oxide Semiconductor (PMOS).
 13. The apparatus of claim10, wherein the offset voltage is equal to a threshold voltage of anN-channel Metal Oxide Semiconductor (NMOS).